On average half the development time for an FPGA is spent on verification
It is possible to significantly reduce this time, and major reductions can be accomplished with just minor adjustments. It is all about Overview, Readability, Maintainability and Reuse at all levels – and you achieve all of this with the right methodology and a good structured architecture.
- Making a simple VHDL test bench step-by-step
- Using VHDL constructs like records, globals, procedures to make a better testbench
- Applying logs, alerts, checkers and BFMs.
- Making an advanced VHDL test bench step-by-step
- Assertions, coverage, debuggers, monitors
- Verification components and testbench architecture for advanced Verification
- Verification reuse and preparations for reuse
- Making testbenches as simple as possible – adapting to the DUT complexity
- Examples and labs using UVVM (Universal VHDL Verification Methodology) – from simple testbenches to advanced verification components.